When IBM announced the "Personal Computer" program, Intel x86 was chosen only because the Zilog Z80 was banned for being "financially problematic".
What a pity, with the {
z80(8bit),
z8000(16bit),
z80000(32bit) } we would have had better computers nowadays.
z80000 includes a memory management unit that provides protected memory and virtual memory addressing with three methods of accessing memory:
- compact mode, only access 16-bit addresses, equivalent to the Z8000's non-segmented mode. bits 31-16 of all virtual addresses
- segmented mode, 32768 segments of 16-bit address, comprising memory from 0-2GB, and 128 segments of 24-bit address, comprising memory from 2GB-4GB); making a total of 32-bit address of accessible memory
- linear mode, 32-bit address accessible memory
Isn't that better than x86-intel? isn't this already "
Unix-style segment"?
For over 30 years intel have promoted nothing but confusion with its lousy definition of "
Intel segment"
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intel-x86 sucks, but evolved during years. It's now on multiprocessing, and both Intel and AMD now have problems with their prose causal-consistency descriptions of the then-current "x86-CC" documentation, which unfortunately turned out to be unsound, forbidding some behavior which actual processors exhibit.
I still remember the early revisions of their "Intel SDM" (2006) which gave an informal-prose model called ‘processor ordering’, which was .... "unsupported" by any example, basically because it doesn't work when you try to implement it, and it doesn't work because it is hard to give a precise interpretation of this description.
Doesn't this sound familiar with intel? when they do something they always do it either badly or too complicated or messed up
Indeed, Intel SDM rev-29 (2008), now they talked about weird memory barrier instructions, now included as "Reads cannot pass LFENCE and MFENCE instructions", but "Writes cannot pass SFENCE and MFENCE instructions”, but writes are now explicitly ordered, but stores are not reordered with other stores so writes by a single processor are observed in the same order by all processors, which unfortunately, it is still problematic, it doesn't tell how to interpret “causality” and says nothing about observations of two stores by those two processors
themselves.
In short, it was still so weak, ugly, complex and potentially catastrophic that you would have given a fsck to that crap. Again. Pretend nothing has happened, touch the kernel as little as possible, as long as it seems working, that's okay
Then someone looked at SPARC. Oh, see, their Total Store Ordering TSO memory model actually works! Why don't we copy it? And Now they are talking about "x86-TSO", a memory model which suffers from neither problem, formalized in HOL4.
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That's intel!
A mediocre company that has spat out a crappy disgusting architecture that has nevertheless been able to sell well; now it's POWER10/11 and RISC-V time, and since they are still with their x86-crap, I hope the company dies a painful but quick death so they won't ruin the future of computing as well like they did during 90s and 2000s.
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